The 8 Bit Iterative Multiplier was designed for my VLSI Design and Simulation course. The goal was to build an 8 bit multiplier which received one 8 bit word at each clock pulse and output the 16 bit product of the current and previous words, all between 3500 and 4000 transistors. The project spanned several months, during which Melissa Fernandez (co-designer) and I designed the sub and full system schematics, mapped the layout for both, tested schematics and layout separately, and finally simulated the complete integrated system. The results were twofold: a final report was drafted for grading (reproduced below) and CIF files were drawn from the simulation to be fabricated. The report received an A letter grade, and MOSIS returned a fully functional microchip.
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